20. - 22.02.2018
Düsseldorf
EMV 2018
Internationale Fachmesse und Kongress für Elektromagnetische Verträglichkeit

 
 
 

Workshop 6

EMC Made Simple 2/2: Designing an Optimal Power Distribution Network (a.k.a. Bypassing and Decoupling)

Termin

Mittwoch, 21.02.2018, 14:00 - 17:00 Uhr

Beschreibung

14:00 EMC Made Simple 2/2: Designing an Optimal Power Distribution Network (a.k.a. Bypassing and Decoupling)
Mark Montrose, Montrose Compliance Serv., Inc., Santa Clara, USA
With advances in semiconductor manufacturing, larger pin count devices, greater power consumption and higher clock speeds, an optimal power distribution network on printed circuit boards is now a primary concern for designers. Signal integrity must be ensured while maintaining electromagnetic compatibility for an intended operating environment, such as telecommunication equipment, information technology or industrial control.
Power plane resonances and lack of energy charge to digital components cause problems that are magnitudes greater than past designs. Understanding how to incorporate capacitive structures in power distribution networks is becoming a mandatory aspect of design engineering along with the PCB layout process. Areas of concern deal with application of use, proper implementation techniques, equivalent series resistance/inductance, minimizing lead and loop inductance, component placement, multi-pole decoupling methodology and of course the use of physical discrete capacitors in addition to buried capacitance is examined.

Referenten

Mr. Mark Montrose
Mark Montrose
Montrose Compliance Serv., Inc., Santa Clara, USA
Mark Montrose is principle consultant of Montrose Compliance Services, Inc. with 36 years of applied, hands-on design experience as a practitioner. He is a professional trainer, consultant and design engineer in all aspects of EMC and authored five popular textbooks. He is a past member of the IEEE EMC Society Board of Directors, past president and founder of the IEEE Product Safety Engineering Society, past Division VI Director and member of the IEEE Board of Directors (2009-2010). He is a iNARTE Master EMC Design Engineer and ISO/IEC 17025 EMC Assessed Test Laboratory.


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