20. - 22.02.2018
EMV 2018
Internationale Fachmesse und Kongress für Elektromagnetische Verträglichkeit


Workshop 3

EMC Made Simple 1/2: System Design-Electromagnetics Made Simple


Mittwoch, 21.02.2018, 09:00 - 12:00 Uhr


09:00 EMC Made Simple 1/2: System Design-Electromagnetics Made Simple
Mark Montrose, Montrose Compliance Serv., Inc., Santa Clara, USA
In order to comply with EMV requirements, one must test a fully-functional system that includes electronic circuitry packaged within either a plastic or metal enclosure. There may be external interconnect cables attached. Computational analysis provides insight on how a system may function, generally using simplified models which may not cover the entire frequency spectrum. This means the engineer could miss operational concerns under unique conditions that may not be anticipated or known.

Printed circuit boards contain multiple components, manufacturing tolerances, interconnects, die shrink plus dozens of other factors that may be unknown or cannot be included within models used during simulation or computational analysis.

This course provides a simplified overview on the complexity of designing a system to achieve EMV. If fundamental rules of design are remembered and implemented, one is able to easily minimize an EMV event. Understanding how to integrate both active and passive elements in an enclosure makes our work as engineers easier. They focus of this workshop is "EMV Made Simple®".


Mr. Mark Montrose
Mark Montrose
Montrose Compliance Serv., Inc., Santa Clara, USA
Mark Montrose is principle consultant of Montrose Compliance Services, Inc. with 36 years of applied, hands-on design experience as a practitioner. He is a professional trainer, consultant and design engineer in all aspects of EMC and authored five popular textbooks. He is a past member of the IEEE EMC Society Board of Directors, past president and founder of the IEEE Product Safety Engineering Society, past Division VI Director and member of the IEEE Board of Directors (2009-2010). He is a iNARTE Master EMC Design Engineer and ISO/IEC 17025 EMC Assessed Test Laboratory.